Semiconductor device including a temperature sensor circuit

ABSTRACT

A semiconductor device including a temperature sensor includes a pull up circuit, a pull down circuit, a first additional current path, and a second additional current path. The pull up circuit is configured to generate a pull up current that contributes to generation of a first output current. The pull down circuit is operably coupled to the pull up circuit at an output node and configured to generate a pull down current that contributes to generation of a second output current. The first additional current path, when enabled, is configured to combine a first additional current with the pull up current to comprise the first output current. The second additional current path, when enabled, is configured to combine a second additional current with the pull down current to comprise the second output current. Respective enablement of the first additional current path and the second additional current path is complementary.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 13/615,245, filed Sep. 13, 2012, now U.S. Pat. No. 9,188,491, issued Nov. 17, 2015, which is a divisional of U.S. patent application Ser. No. 12/818,889, filed Jun. 18, 2010, now U.S. Pat. No. 8,292,503, issued Oct. 23, 2012, which is a divisional of Ser. No. 11/839,900, filed Aug. 16, 2007, now U.S. Pat. No. 7,771,115, issued Aug. 10, 2010, the entire disclosure of each of which is hereby incorporated herein by this reference.

FIELD

Embodiments of the present invention relate generally to temperature sensors and, more particularly, to determining temperature by obtaining a linear output of temperature values.

BACKGROUND

In modern high frequency integrated circuits, operating temperature has become increasingly important. Generally, semiconductor devices are specified to operate in a certain temperature range within which the device has been characterized. Additional heat created on a semiconductor device due to higher operating frequencies may affect power consumption and system performance. Temperature sensors may be implemented in a device to report the current temperature to a controller, which may modify operational parameters that affect temperature such as temporarily adjusting clock rate or running the device in a different power mode. These adjustments may bring the temperature back within the desired temperature range for the device and the operational parameters may then be returned to their previous values.

For semiconductor devices such as Dynamic Random Access Memory (DRAM) devices, a temperature sensing circuit may be used to monitor temperature in order to control the refresh rate of the memory cells. With DRAM devices, a charge representing stored data may be lost due to leakage, and therefore must be periodically refreshed since charge leakage is very dependant on temperature. As operating temperature is variable, maintaining a constant refresh rate may result in either data loss or a waste of power if the refresh rate is performed at a different rate than the temperature demands. As temperature increases, charge leakage also increases, and the memory cell charge must be refreshed more frequently. As temperature decreases, charge leakage also decreases, and refreshing may be performed less frequently. As a result of these problems, it is important that a temperature sensor accurately and efficiently determine the current operating temperature.

One conventional approach to temperature sensing includes comparing an output voltage (Vout) of a circuit to a reference voltage (Vref) and enabling a switch if the output voltage (Vout) is greater than the reference voltage (Vref). By monitoring the percentage of times (X %) that the switch is enabled, a number or measure of output counts can be calculated and stored in a counter, which may be set to represent, for example, one count per 1° Celsius. The temperature then may be calculated by comparing the number or measure of output counts in the counter by some offset constant.

As a result, there is a need for a temperature sensor that can more efficiently obtain a set of linear temperature readings while adding little additional circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a temperature sensor.

FIG. 2 is a graph illustrating variations of coefficients across a temperature range for a non-linear temperature algorithm.

FIG. 3 is a graph illustrating a measure of temperature sensor counts compared to a plot of a measure of ideal counts of a non-linear temperature sensor.

FIG. 4 is a graph illustrating coefficient variations of numerator and denominator coefficients varying across a temperature range for a linear temperature algorithm.

FIG. 5 is a graph illustrating a measure of temperature sensor output counts compared to a plot of a measure of ideal counts of a temperature sensor when a measure of total clocks is increased and the measure of output counts is linear across a temperature range.

FIG. 6 is a graph illustrating a measure of temperature sensor counts compared to a plot of a measure of ideal counts of a temperature sensor, in accordance with an embodiment of the present invention.

FIG. 7 is a circuit diagram of a temperature sensor, in accordance with an embodiment of the present invention.

FIG. 8 is a graph illustrating a measure of temperature sensor counts that are linear across a temperature range compared to a plot of a measure of ideal counts of a temperature sensor, in accordance with an embodiment of the present invention.

FIG. 9 is a diagram of an electronic system including a memory device having a temperature sensor, in accordance with an embodiment of the present invention.

FIG. 10 is a diagram of a semiconductor wafer including a plurality of semiconductor devices including a temperature sensor, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

In the following description, embodiments of a circuit and a method are set forth for a temperature-sensing algorithm in both non-linear and linear forms. Also as set forth are embodiments of a circuit and method implementing an algorithm to overcome shortcomings of both conventional non-linear and conventional linear algorithms. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical, and electrical changes may be made within the scope of the present invention.

In this description, circuits and functions may be shown in block diagram form in order not to obscure the present invention in unnecessary detail. Furthermore, specific circuit implementations shown and described are only examples and should not be construed as the only way to implement the present invention unless specified otherwise herein. Block definitions and partitioning of logic between various blocks represent a specific implementation. It will be readily apparent to one of ordinary skill in the art that the various embodiments of the present invention may be practiced by numerous other partitioning solutions. For the most part, details concerning timing considerations, and the like, have been omitted where such details are not necessary to obtain a complete understanding of the present invention in its various embodiments and are within the abilities of persons of ordinary skill in the relevant art.

FIG. 1 is a circuit diagram of a temperature sensor 50 including a pull up circuit 100 that generates a pull up current (Ipup) and a pull down circuit 200 that generates a pull down current (Ipdn). The average value of the pull down current (Ipdn) is defined as the value of Ipdn with the switch 250 enabled multiplied by the percentage of time (X %) that the switch 250 is enabled. Temperature sensor output data is generated and stored in a counter and decoder module 285 as a ratio of the number of times (Output Counts) that the switch 250 is enabled to a full cycle of readings (Total Clocks) in order to generate a final temperature estimate signal (TempReadout). The temperature estimate signal (TempReadout) can be further interpreted by external circuitry to modify operational parameters, such as DRAM refresh rate, in response to a determined temperature change. An example of such external circuitry is a refresh controller that adjusts the refresh rate of a memory device based upon the current temperature information provided by the temperature estimate signal (TempReadout).

As an example, if a measure of Output Counts are set to represent 1° Celsius per count, the temperature estimate signal (TempReadout) can be determined by:

  TempReadout = Output Counts − Counts Offset  where:   Output Counts = Enbl * Total Clocks.   where:    Enbl is the decimal equivalent of X%, i.e., X% / 100; and    Total Clocks a measure of units of time. By the nature of a delta sigma converter:   Ipup = Enbl * Ipdn  therefore:   Enbl = Ipup / Ipdn  and where:   Ipup = n * Vt * lnK / R1   Ipdn = A * Vdl / L * R1  solving for Enbl:   Enbl = Ipup / Ipdn = (n * Vt * lnK * L) / (A * Vd1)  therefore:   Output Counts = (n * Vt * lnK * L) / (A * Vdl) * Total Clocks

-   -   where n is a process constant parameter substantially close to         1, Vt is the thermal voltage of the transistors in the pull up         circuit 100 and the pull down circuit 200, and Vd1 is the         one-times diode forward biasing voltage.

Accordingly, when temperature increases, Vt increases at a rate of approximately 0.085 mV/° C., and Vd1 decreases at a rate of approximately −1.63 mV/° C. in a typical process. For a typical process where, for example, the values of L=6, K=24, A=1.33, the Total Clocks to obtain a measure of Output Counts that are 1° Celsius per count is 245.

According to the equations above with this temperature sensor, the numerator parameter of Enbl, (n*Vt*ln K*L), will increase when temperature increases and the denominator parameter of Enbl, (A*Vd1), will decrease when temperature increases. Both numerator and denominator parameters will be linear across the temperature when viewed separately as is represented in FIG. 2. However, when combining both parameters to form Enbl, (n*Vt*ln K*L)/(A*Vd1), Enbl will not be linear. As a result, when combining Enbl with the Total Clocks, the Output Counts will also be nonlinear as is shown in FIG. 3.

FIG. 3 is a graph illustrating a measure of a temperature sensor Output Counts compared with a plot of a measure of ideal counts across a temperature range for the non-linear temperature sensor 50. With these settings, Output Counts can change about 1° Celsius per count at temperatures near 90° Celsius. However, at low temperatures, the measure of Output Counts is no longer linear. In order to obtain a linear output, the Enbl needs to be linear across a range of temperatures. Accordingly, a linear voltage over a constant voltage is used. The constants A, L, and K of the temperature sensor 50 may be configured such that (Ipup+Ipdn) is the bandgap reference and is substantially constant across the temperature range. In order to generate a linear Enbl across the temperature range: Set Enbl=Ipup/(Ipup+Ipdn)=n*Vt*ln K*L/(A*Vd1+n*Vt*ln K*L)

and configure constants A, K, and L such that:

-   -   (n*Vt*ln K*L) is a positive value; and     -   (A*Vd1+n*Vt*ln K*L) is constant.     -   Accordingly, Enbl becomes linear across the temperature range         when L=6, K=24, A=1 and the Total Clocks=735 for 1° Celsius per         count.

FIG. 4 is a graph illustrating coefficient variations of numerator and denominator coefficients varying across the temperature range for a linear temperature algorithm. In FIG. 4, the numerator parameter (n*Vt*ln K*L) and denominator parameter (A*Vd1+n*Vt*ln K*L) are separately graphed to illustrate the linear relationship therebetween. The numerator parameter, (n*Vt*ln K*L), increases linearly when the temperature increases and the first and second terms within the denominator parameter (A*Vd1+n*Vt*ln K*L) increase and decrease, respectively, at substantially the same rate resulting in a substantially constant denominator over the temperature range.

FIG. 5 is a graph illustrating a measure of temperature sensor Output Counts compared to a plot of a measure of ideal counts as the measure of Total Clocks is increased resulting in the measure of Output Counts remaining linear across the temperature range. While such a configuration results in an increased temperature sensor accuracy across the temperature range, additional clocks, for example, 735 Total Clocks are needed to achieve the linear result when, for example, 245 Total Clocks were needed for the non-linear temperature sensor 50. Unfortunately, nearly three times as many units of time are required to obtain an accurate linear result according to such an approach.

The present embodiment utilizes an algorithm that solves the drawback of a conventional linear temperature sensor and a conventional non-linear sensor by obtaining a linear output without increasing the Total Clocks by setting:

 Output Counts = Enbl * Total Clocks − Offset Constant set: Enbl = 3 * Ipup / (Ipup+Ipdn) Total Clocks is 245 for Output Counts to be 1° Celsius per count, then:  Output Counts = 3 * Ipup / (Ipup+Ipdn) * 245 − 245 which simplifies to:  Output Counts = 245 * (2 * Ipup − Ipdn) / (Ipup+Ipdn)    (1)

Accordingly, the pull down current (Ipdn) and the pull up current (Ipup) may be set to increase and decrease inversely at substantially the same rate in order for the denominator portion of Equation (1), (Ipup+Ipdn), to be constant across the temperature range, and the numerator portion of Equation (1), (245*(2*Ipup−Ipdn)), to increase linearly across the temperature range.

FIG. 6 is a graph illustrating temperature sensor counts compared to a plot of a measure of ideal counts of a temperature sensor, in accordance with an embodiment of the present invention. Because the denominator is constant across the temperature range, and the numerator is linear across the temperature range, the output given by Equation (1) and illustrated in FIG. 6 is also linear across the temperature range.

FIG. 7 is a circuit diagram of a temperature sensor, in accordance with an embodiment of the present invention. In FIG. 7, a circuit realization of the above-described algorithm is illustrated in a temperature sensor circuit 290. Temperature sensor circuit 290 includes temperature sensitive circuit elements such as transistors, resistors, and diodes. Temperature sensor circuit 290 further includes a pull down circuit 400 that may be configured to generate a pull down current (Ipdn). This embodiment also includes a pull up circuit 300 that may create a pull up current (Ipup). The pull down circuit 400 includes a resistor 410, which is related to the resistance of a resistor 320 in the pull up circuit 300 by a constant (L). The pull down circuit includes at least one current mirror with transistors 425 and 430 with the at least one current mirror having a ratio (A). The pull up circuit 300 may include a first diode 310 and a second diode 315, wherein the size of the second diode 315 is related to the size of the first diode 310 by a constant (K). When temperature increases, thermal voltage (Vt) increases at a rate of approximately 0.085 mV/° C., and one-times diode forward biasing voltage (Vd1) decreases at a rate of approximately −1.63 mV/° C. in an illustrative process. Accordingly, the pull up current (Ipup) and pull down current (Ipdn) are: Ipup=n*Vt*ln K/R1 Ipdn=A*Vd1/L*R1

where n is a process constant parameter substantially equal to 1.

The embodiment of FIG. 7 for temperature sensor circuit 290 may also include a first additional current path 302 including a first switch 350 serially coupled to a first transistor 340 with the first switch 350 and the first transistor 340 coupled in parallel with the pull up circuit 300. The current through the first transistor 340 is combined with the pull up current (Ipup) to form output current (Ia) at an output node (N). The temperature sensor circuit 290 may also include a second additional current path 402 including a second switch 450 serially coupled to a second transistor 435 with the second switch 450 and the second transistor 435 coupled in parallel with the pull down circuit 400. The current through the second transistor 435 is combined with the pull down current (Ipdn) to form output current (Ib) at the output node (N).

Comparator 470 compares an output voltage (Vout) to a reference voltage (Vref) from a reference voltage generator 490 in order to control enablement of the first switch 350 and the second switch 450. When output voltage (Vout) is greater than reference voltage (Vref), the second switch 450 is enabled and the first switch 350 is disabled. When reference voltage (Vref) is greater than output voltage (Vout), the first switch 350 is enabled and the second switch 450 is disabled. Inverter 475 causes the first switch 350 and the second switch 450 to be complementary enabled such that the second switch 450 is enabled a percentage of the time (X %), and the first switch 350 is enabled a percentage of the time (100−X %).

The temperature sensor output data is generated and stored in a counter and decoder module 485 as a ratio of the number of times (Output Counts) that the switch 350 is enabled to a full cycle of readings (Total Clocks) in order to generate a final temperature estimate signal (TempReadout). The temperature estimate signal (TempReadout) can be further interpreted by external circuitry to modify operational parameters, such as DRAM refresh rate, in response to the determined temperature change. An example of such external circuitry is a refresh controller that adjusts the refresh rate of a memory array on a memory device based upon the current temperature information provided by the temperature sensor circuit 290. If Output Counts are set to represent 1° Celsius per count, the temperature estimate signal (TempReadout) can be determined by:

 TempReadout = Output Counts − Counts Offset where:  Output Counts = Enbl * Total Clocks   Enbl is the decimal equivalent of X%, i.e., Enbl = X% / 100; and   Total Clocks is a measure of units of time.

By nature of the delta sigma converter:

 Ia = Ib where:  Ia = Ipup + (1 − Enbl) * Ipup  Ib = Ipdn + Enbl * Ipdn solving for Enbl and simplifying:  Enbl = (2 * Ipup − Ipdn) / (Ipup + Ipdn) solving for Output Counts:  Output Counts = Enbl * Total Clocks when setting Total Clocks = 245:  Output Counts = 245 * (2 * Ipup − Ipdn) / (Ipup + Ipdn)   (2)

Equation (2) shows an Output Counts that is on the same order as in Equation (1), which demonstrates that the circuit realization of the above algorithm results in a linear output generated with a quantity of Total Clocks being on the same order as the quantity of Total Clocks for the nonlinear output. Thus, the linear output over the temperature range with 245 Total Clocks is a major improvement over the conventional temperature sensor, which previously had to trade more Total Clocks for better linearity. Accordingly, the now-derived temperature estimate signal (TempReadout) can be used by other circuits or modules to modify behavior and operational parameters. The temperature estimate signal (TempReadout) may be configured as a group of signals indicating various temperature points where one of the signals is active at any given time indicating a current temperature. Alternatively, the temperature estimate signal (TempReadout) may be configured as an analog signal indicating the temperature.

FIG. 8 is a graph illustrating a measure of temperature sensor counts that are linear across a temperature range when compared to a plot of a measure of ideal counts of a temperature sensor, in accordance with an embodiment of the present invention. The plots illustrate simulation results of the circuit showing the measure of Output Counts of the simulated temperature sensor circuit 290 compared with the output for the algorithm from FIG. 6. As illustrated, the simulation results very closely approximate the linearity of the measure of ideal counts over the temperature range.

FIG. 9 is a block diagram of an electronic system including a memory device having a temperature sensor, in accordance with an embodiment of the present invention. An electronic system 500 includes at least one of an input device 510 and an output device 520 and further includes at least one processor 530 and at least one memory device 540. The memory device 540 includes the temperature sensor circuit 290 as described herein in communication with a refresh controller 550 to control the refresh rate of a semiconductor memory array 560.

FIG. 10 is a diagram of a semiconductor wafer including a plurality of semiconductor devices including at least one temperature sensor, in accordance with an embodiment of the present invention. A semiconductor wafer 600 includes a plurality of semiconductor devices 650 incorporating the temperature sensor circuit 290 (not shown in FIG. 10) as described herein. Of course, it should be understood that the plurality of semiconductor devices 650 may be fabricated on substrates other than a silicon wafer, such as, for example, a Silicon On Insulator (SOI) substrate, a Silicon On Glass (SOG) substrate, a Silicon on Sapphire (SOS) substrate, a gallium arsenide wafer, an indium phosphide wafer, or other bulk semiconductor substrate. As used herein, the term “wafer” includes and encompasses all such substrates.

CONCLUSION

Embodiments described herein disclose a temperature sensor device for obtaining a linear set of temperature readings over a temperature range while doing so with fewer units of time than with prior temperature sensing circuits. An embodiment disclosed herein comprises a pull down circuit configured to generate a pull down current, and a pull up circuit configured to generate a pull up current. The pull up circuit and pull down circuit are coupled to a plurality of switches configured to generate a first output current and a second output current. The pull up circuit and the pull down circuit each comprise temperature sensitive circuit elements such as resistors, transistors, and diodes.

In order to obtain a linear temperature reading over a range of temperatures, the temperature sensitive circuit elements may be configured such that the average values of the first output current and the second output current are substantially the same. The temperature sensitive circuit elements may also be configured such that the pull up current and the pull down current inversely change with temperature at substantially the same rate. A comparator, that compares a reference voltage and an output voltage, controls the enablement of the first switch and the second switch. The first switch and the second switch are complementary enabled in response to an output signal dependent on temperature such that the second switch is enabled a percentage of time (X %) and the first switch is enabled a percentage of time (100−X %).

Another embodiment disclosed herein comprises a method of sensing temperature, configuring a plurality of temperature sensitive circuit elements, such as resistors, transistors, and diodes to form a pull down circuit and a pull up circuit in order to generate a pull down current and a pull up current respectively. The method of sensing temperature further comprises comparing an output voltage with a reference voltage to control the enabling of a plurality of switches in a complementary manner. Configuring the plurality of temperature sensitive circuit elements further comprises forming a first output current and a second output current in such a manner that the average values of the first output current and the second output current are substantially equal. Configuring the plurality of temperature sensitive circuit elements further comprises having the pull up current and the pull down current set to change with temperature inversely at the same rate in order to obtain a linear temperature reading.

Another embodiment disclosed herein comprises a semiconductor device including at least one temperature sensor. Yet another embodiment comprises an electronic system including at least one input device, at least one output device, at least one processor, and at least one memory device. The at least one memory device and/or processor comprises at least one temperature sensor according to the present invention described herein. The at least one temperature sensor may communicate with a refresh controller which may control the refresh rate of a semiconductor memory array. Yet a further embodiment disclosed herein comprises at least one semiconductor device including at least one temperature sensor according to the present invention fabricated on a semiconductor wafer.

Although the foregoing description contains many specifics, these are not to be construed as limiting the scope of the present invention, but merely as providing certain exemplary embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions, and modifications to the invention, as disclosed herein, which fall within the meaning and scope of the claims are encompassed by the present invention. 

What is claimed is:
 1. A semiconductor device comprising: first and second power lines; an output node; a pull up circuit comprising a first transistor coupled between the first power line and the output, node, the pull up circuit configured to generate a pull up current (Ipup); a pull down circuit comprising a second transistor coupled between the second power line and the output node, the pull down circuit configured to generate a pull down current (Ipdn); a first additional current path comprising a third transistor and a first switch coupled in series between the first power line and the output node, the first additional current path configured to generate a first additional current that combines with the pull up current (Ipup) to generate a first output current (Ia); and a second additional current path comprising a fourth transistor and a second switch coupled in series between the second power line and the output node, the second additional current path configured to generate a second additional current that combines with the pull down current (Ipdn) to generate a second output current (Ib).
 2. The semiconductor device of claim 1, wherein the first switch and the second switch are configured to be enabled complementarily.
 3. The semiconductor device of claim 1, wherein the first transistor and the third transistor are coupled in common at their respective gates, and the second transistor and the fourth transistor are coupled in common at their respective gates.
 4. The semiconductor device of claim 2, further comprising a comparator including: a first input node coupled to the output node; and a second input node supplied with a reference voltage.
 5. The semiconductor device of claim 4, wherein an output of the comparator is fed back to each of the first switch and the second switch to enable the first switch and the second switch complementarily.
 6. The semiconductor device of claim 1, wherein each of the first transistor and the third transistor is of a first channel type, and each of the second transistor and the fourth transistor is of a second channel type.
 7. The semiconductor device of claim 6, wherein the first transistor and the third transistor have a ratio of 1:1, and the second transistor and the fourth transistor have a ratio of 1:1.
 8. The semiconductor device of claim 4, further comprising a counter and decoder module operably coupled to the comparator to receive an output signal, the counter and decoder module configured to generate a temperature estimate signal in response to the output signal of the comparator.
 9. The semiconductor device of claim 8, wherein the counter and decoder module are configured to generate the temperature estimate signal based, at least in part, on the number of times (Output Counts) that a single one of the first switch and the second switch is enabled for a full cycle of readings (Total Clocks) by the counter and decoder module.
 10. The semiconductor device of claim 9, wherein the Output Counts are approximately equal to Output Counts=Total Clocks*(2*Ipup−Ipdn)/(Ipup+Ipdn).
 11. The semiconductor device of claim 10, wherein each change in the Output Counts as the counter and decoder module increments the Output Counts is approximately equal to 1 degree Celsius per count.
 12. The semiconductor device of claim 9, wherein the counter and decoder module are configured to generate the temperature estimate signal based further by subtracting a predetermined offset number of counts from the Output Counts.
 13. The semiconductor device of claim 1, wherein the first transistor is configured to provide a first temperature sensitive current and the second transistor is configured to provide a second temperature sensitive current.
 14. A semiconductor device, comprising: first and second power lines; an output node; a pull up circuit comprising a first transistor coupled between the first power line and the output node; a pull down circuit comprising a second transistor coupled between the second power line and the output node; a first additional current path comprising a third transistor and a first switch coupled in series between the first power line and the output node; and a second additional current path comprising a fourth transistor and a second switch coupled in series between the second power line and the output node, wherein the first transistor is configured to provide a first temperature sensitive current and the second transistor is configured to provide a second temperature sensitive current.
 15. The semiconductor device of claim 14, wherein the third transistor is configured to provide a third temperature sensitive current proportional to the first temperature sensitive current, and the fourth transistor is configured to provide a fourth temperature sensitive current proportional to the second temperature sensitive current.
 16. The semiconductor device of claim 4, wherein: the first additional current path generates the first additional current responsive to an output of the comparator; and the second additional current path generates the second additional current responsive to the output of the comparator.
 17. The semiconductor device of claim 16, wherein: the first additional current, when the first switch is enabled, is approximately equal to the pull up current (Ipup); and the second additional current, when the second switch is enabled, is approximately equal to the pull down current (Ipdn).
 18. The semiconductor device of claim 17, wherein the first output current (Ia) and the second output current (Ib) have average values approximately equal to: Ia=Ipup+(1−Enbl)*Ipup; and Ib=Ipdn+Enbl*Ipdn, wherein Enbl is a decimal equivalent of a percentage of time that the second switch of the second additional current path is enabled responsive to the output of the comparator, and (1−Enbl) is a decimal equivalent of a percentage of time that the first switch of the first additional current path is enabled responsive to the output of the comparator.
 19. The semiconductor device of claim 18, wherein: the pull up circuit further comprises: a fifth transistor and a sixth transistor having their gates controllable by a first comparator, the gates of the fifth transistor and the sixth transistor further coupled with gates of the first transistor and the third transistor; a first diode operably coupled to a first input of the first comparator; and a second diode and a first resistor serially coupled to a second input of the first comparator; and the pull down circuit further comprises: a seventh transistor and an eighth transistor having their gates controllable by a second comparator, the gates of the seventh transistor and the eighth transistor further coupled with gates of the second transistor and the fourth transistor; a second resistor coupled to a second input of the second comparator, wherein a first input of the second comparator is coupled with the first input of the first comparator of the pull up circuit; and a first current mirror coupled between the eighth transistor and the second additional current path.
 20. The semiconductor device of claim 19, wherein the pull up current (Ipup) and the pull down current (Ipdn) are approximately equal to the following equations: Ipup=(n*Vt*ln K)/R, wherein n is a process constant parameter, Vt is a thermal voltage of the first transistor, K is a constant for a size ratio for first and second diodes of the pull up circuit, and R is a value of the first resistor of the pull up circuit; and Ipdn=(A*Vd1)/(L*R), wherein A is a ratio for the current mirror of the pull down circuit, Vd1 is a diode forward biasing voltage for one of the first and second diodes of the pull up circuit, and L is a constant for the second resistor of the pull down circuit related to the value R of the first resistor of the pull up circuit. 